By David R. Stauffer, Jeanne Trinko Mechler, Michael Sorna, Kent Dramstad, Clarence R. Ogilvie, Amanull
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Additional resources for High Speed Serdes Devices and Applications
0 = operation not in progress, not yet complete, or no receiver is detected; 1 = operation is complete and a receiver is detected TXxRCVRDETFALSE Out Transmit Receiver Detect False Status: Asserted while TXxRCVRDETEN is high if the result of the Transmit Receiver Detect operation is that a receiver is not detected. 0 = operation not in progress, not yet complete, or receiver is detected; 1 = operation is complete and a receiver is not detected In Transmit Power State: Power down signal which powers off the Transmitter slice.
When active, register 0x0F for each RX link can be read to determine updated status Signal Integrity HSSEYEQUALITY TXxD[19:0] TXxOBS TXxTS TXxPRBSEN TXxPRBSRST TXxBYPASS TXxJTAGAMPL[1:0] TXxJTAGTS TXxBSIN TXxBEACONEN TXxRCVRDETEN TXxDCLK Port Data TXxO[P,N] PRBS Generator JTAG TXxBSOUT PCI Express Support TXxRCVRDETTRUE TXxRCVRDETFALSE TXxELECIDLE TXxPWRDWN TXxSTATEL1 Power Fig. 2 Transmitter slice specific core pin definitions Pin name Type Description Port data signals TXxD[19:0] In Parallel input data.
It indicates lock was achieved at least once 3:2 R 00 Unused 4 R 0 DFE training complete This register is set when the DFE logic determines that its H coefficients have converged since reset. 0=initial DFE convergence not yet achieved, 1=initial DFE convergence achieved 5 R 0 Eye Width Error Flag: 0=normal: Measured Data Eye Width at or above interrupt threshold set in the Digital Eye Control Register (reg 0x09); 1=error: Measured Data Eye Width below interrupt threshold set in the Digital Eye Control Register (reg 0x09) 6 R 0 Eye Amplitude Error Flag: 0=normal: Measured Data Eye Height at or above interrupt threshold set in the Digital Eye Control Register (reg 0x09); 1=error: Measured Data Eye Height below interrupt threshold set in the Digital Eye Control Register (reg 0x09) 15:7 R 0x000 0x0000 Internal Status Register This register is used to report the status of certain internal operations.
High Speed Serdes Devices and Applications by David R. Stauffer, Jeanne Trinko Mechler, Michael Sorna, Kent Dramstad, Clarence R. Ogilvie, Amanull